Folded bitline architecture has, for years, been the standard for the dynamic random access memory (DRAM) arrays. Because reliable operation of a DRAM array having a folded bitline architecture requires that the capacitors of individual DRAM cells see a maximum of no more than half the power supply voltage across the capacitor plates, optimum cell capacitance can be achieved by utilizing a capacitor dielectric layer having a thickness that reliably withstands breakdown voltages of only slightly more than half the power supply voltage.
Contemporary DRAM memories require a high degree of redundancy (i.e., extra array columns and extra array rows which can be used to replace defective columns and rows) in order to improve manufacturing yields Antifuses have been suggested for use as nonvolatile programmable memory elements to store logic states which would be used in DRAMs for row and column redundancy implementation. An antifuse is, by definition, a device which functions as an open circuit until programmed to be a permanent short circuit. Ideally, antifuses for redundancy implementation would be constructed in the same manner as the cell capacitors in the DRAM array. Although various dielectrics have been utilized in anti-fuses, an oxide-nitride-oxide (ONO) dielectric, optimized as an antifuse able to withstand full power supply voltage (commonly denoted V.sub.CC) has proven to be very reliable. Oxide-nitride-oxide (ONO) dielectric layers are also commonly used in contemporary DRAMs. It is a well-known fact that once a capacitor in a DRAM cell has been subjected to excessive voltage, it will be permanently unusable due to the development of a resistive short in the capacitor dielectric. As a result of the short, the capacitor will no longer be able to maintain a charge.
Because of the fact that CMOS logic typically requires full power supply voltage, and because the capacitors in contemporary DRAMs are designed to reliably withstand only half the power supply voltage, nonvolatile memory cells constructed with anti-fuses cannot be incorporated in a DRAM memory unless the dielectric layer used in the anti-fuses is thicker than that used in the DRAM cells. A two-thickness dielectric process would add cost to the manufacturing process.
What is needed is a new nonvolatile memory cell which incorporates anti-fuses operable at less than full power supply voltage, and which provides full CMOS output voltage levels. In addition, the new nonvolatile memory cell must make use of ONO dielectric layers which are optimized as capacitor dielectrics, rather than antifuse dielectrics. Such a cell could be utilized not only to implement redundancy in a DRAM array with little or no additional processing steps, but also for the construction of programmable logic devices requiring lower programming voltages.